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High-Speed SerDes & IO

Four-level PAM eye diagram representative of PAM4 serial signaling.
Four-level PAM eye diagram, illustrating the multiple decision regions and reduced vertical margin characteristic of PAM4 signaling. Image source: Wikimedia Commons, CC BY 2.5.
30-second intuitionA high-speed SerDes converts wide low-rate parallel data into a very fast serial waveform, sends it through a lossy channel, and reconstructs both data and timing at the receiver. At 100+ Gb/s-class operation, the design problem spans analog circuits, clocking, digital logic, channel physics, adaptation, coding, and lab correlation.
parallel data→serializer + TX FFE→channel→RX CTLE / ADC / DFE→CDR→deserializer

Part I — SerDes architecture

1. What is a SerDes?

A serializer/deserializer pair enables very high aggregate data rate while limiting pin count.

A typical transmitter contains

A receiver contains

2. Unit interval

For symbol rate $R_s$,

\[UI=\frac{1}{R_s}.\]

At 100 GBd,

\[UI=10\ \mathrm{ps}.\]

A few picoseconds of jitter can therefore consume a large fraction of the available timing margin.

3. NRZ and PAM4

NRZ carries one bit per symbol with two levels.

PAM4 carries two bits per symbol with four levels.

For bit rate $R_b$,

\[R_s=R_b\]

for NRZ and approximately

\[R_s=\frac{R_b}{2}\]

for uncoded PAM4.

PAM4 lowers Nyquist frequency for a given bit rate but produces three eyes and much smaller vertical separation.

For equally spaced ideal PAM4 levels, the eye height is roughly one-third of the full swing before noise and distortion.

At 100+ Gb/s per lane or comparable aggregate architecture, fundamental problems include

The boundary between “analog” and “digital” becomes increasingly architectural.

Part II — Transmitter

5. Serializer

A serializer multiplexes lower-rate data streams into a high-rate stream.

Architectures include

The choice affects

6. High-speed digital logic

SerDes uses fast digital blocks such as

CML can be used at the highest clock rates, while CMOS logic dominates lower-rate support functions.

Important digital concerns include setup/hold time, clock skew, metastability, duty cycle, and power.

7. TX output drivers

Common high-speed driver styles include

The driver must meet

For PAM4, driver linearity and level spacing are substantially more important than for two-level NRZ.

8. TX feed-forward equalization

A TX FFE creates a weighted sum of delayed data symbols:

\[y[n]=\sum_{k=0}^{N-1}c_kx[n-k].\]

A simple precursor/main/postcursor system is

\[y[n] = c_{-1}x[n+1] +c_0x[n] +c_1x[n-1].\]

The taps pre-distort the transmitted waveform so that the combination of TX and channel has a cleaner pulse response.

9. De-emphasis and pre-emphasis

Serial-data eye pattern measured with transmitter pre-emphasis.
Measured serial-data eye with transmitter pre-emphasis, illustrating how equalization reshapes the waveform to compensate channel loss. Image source: Wikimedia Commons.

De-emphasis reduces steady-state amplitude relative to transition amplitude.

Pre-emphasis increases transition energy.

Both are manifestations of transmitter equalization designed to compensate frequency-dependent channel loss.

The cost is increased driver complexity and potentially increased power or peak swing.

Part III — Receiver front end

10. RX termination

The input termination controls

At high speed, termination accuracy may require calibration because resistor values vary over PVT.

11. CTLE

A continuous-time linear equalizer introduces more gain at high frequency than low frequency.

A simplified transfer function is

\[H(s)=A_0 \frac{1+s/\omega_z} {1+s/\omega_p}, \qquad \omega_z<\omega_p.\]

Its boost is roughly

\[20\log_{10} \left( \frac{\omega_p}{\omega_z} \right)\]

over the appropriate region.

CTLE is power efficient but amplifies high-frequency noise as well as signal.

12. VGA and AGC

A variable-gain amplifier helps keep internal signal swing in a useful range.

Automatic-gain control must balance

For PAM4, gain errors also affect level spacing and slicer thresholds.

13. Slicers

A slicer compares the equalized waveform against a decision threshold.

NRZ nominally needs one primary threshold.

PAM4 needs three decision thresholds.

Comparator offset and threshold mismatch therefore become more important in PAM4 receivers.

Calibration can correct threshold and offset errors.

14. ADC-based receiver

For ADC/DAC architecture, ENOB/SNDR/SFDR, sampling-jitter limits, time interleaving, and converter measurements, see ADC & DAC — Data Converters.

An ADC-based SerDes samples the waveform with multiple bits of resolution and performs substantial equalization digitally.

Advantages include

Costs include

Part IV — DFE and adaptation

15. Decision-feedback equalization

A DFE subtracts estimated post-cursor ISI using previous decisions:

\[y[n] = x[n] - \sum_{k=1}^{N}b_k\hat d[n-k].\]

Because it does not directly amplify channel noise, DFE can be highly effective for post-cursor ISI.

Its main challenge is feedback timing and error propagation.

16. DFE loop timing

The first DFE tap may need to close within approximately one UI.

Architectural solutions include

At extreme rates, timing feasibility becomes a first-order architecture constraint.

17. Adaptive equalization

Adaptive loops estimate equalizer settings during operation.

Possible controlled parameters include

Adaptation improves tolerance to channel and PVT variation but increases state-space and validation complexity.

18. LMS-based equalizer adaptation

A common update is

\[w_k[n+1] = w_k[n] + \mu e[n]x[n-k].\]

For decision-directed adaptation, the error may be

\[e[n]=\hat d[n]-y[n].\]

Practical implementation requires finite-word-length analysis, update scheduling, coefficient limits, and convergence verification.

19. Sign-sign and low-complexity adaptation

To reduce digital power, the update may use only the sign of error and input.

This reduces multipliers but changes convergence behavior.

In high-speed IO, a slightly less statistically efficient adaptation law can be preferable if it materially improves PPA.

20. Background adaptation

Background adaptation tracks slow PVT and channel changes while traffic continues.

The control loop must avoid fighting other loops, such as

Loop interaction is a major system-level verification issue.

Part V — Clock and data recovery

21. CDR purpose

The receiver generally does not receive a separate sampling clock. CDR extracts timing from data transitions.

The core objective is

\[\boxed{ \text{place sampling phase near the center of the data eye}. }\]

22. CDR architectures

Common architectures include

The architecture determines loop dynamics, jitter tracking, hardware rate, and interaction with equalization.

23. Bang-bang phase detector

The Alexander/bang-bang detector outputs early/late information rather than a linear phase-error magnitude.

It is simple and robust but nonlinear.

The loop may exhibit limit cycles and behavior not captured by a purely linear PLL model.

24. Linear CDR model

A linearized CDR can often be represented as

\[\Phi_{out}(s) = H_{CDR}(s)\Phi_{data}(s) + H_n(s)N(s).\]

The loop bandwidth determines which data-phase variations are tracked and which appear as jitter error.

25. Jitter tolerance and transfer

Three common clock-performance views are

These are protocol-dependent compliance concepts as well as circuit-design concerns.

26. Baud-rate CDR

A baud-rate CDR extracts timing using one sample per symbol plus suitable error information.

It can save sampling power compared with oversampling CDRs.

However, equalization and timing estimation become more tightly coupled.

Part VI — PLLs and clock distribution

27. TX PLL

A TX PLL multiplies a stable reference to the serializer clock.

The clock phase noise directly contributes to transmitted jitter.

The system must budget contributions from

28. Clock dividers

High-speed divider architectures include

Divider topology is constrained by maximum clock rate, power, and phase-noise contribution.

29. Phase interpolators

A phase interpolator creates an output phase between reference clock phases.

It is widely used in CDR and multi-lane deskew.

Important nonidealities include

Part VII — Channel and system requirements

30. Channel impulse response

A serial channel can be represented as

\[y(t)=h(t)*x(t)+n(t).\]

Reflections and frequency-dependent loss create a pulse response that extends across multiple UIs, producing ISI.

Equalization aims to shorten or invert the relevant part of $h(t)$ without unacceptable noise enhancement.

31. Channel operating margin

A channel specification translates loss, reflections, crosstalk, transmitter behavior, receiver behavior, and equalization capability into an overall margin.

A physically attractive S-parameter plot is not sufficient by itself; the channel must be evaluated with the intended TX/RX architecture.

See Signal Integrity & Power Integrity.

32. BER and bathtub curves

BER is

\[BER=\frac{N_{error}}{N_{bits}}.\]

A bathtub curve plots estimated BER versus sampling phase.

Its horizontal opening at the target BER is a powerful timing-margin metric.

For PAM4 there are multiple eyes and error mechanisms, so BER/SER analysis becomes more involved.

33. PAM4 transmitter linearity

PAM4 requires accurate intermediate levels.

Useful metrics include

A nonlinear output stage can compress outer levels and reduce minimum eye height.

34. PAM4 receiver thresholds

With ideal normalized levels $-3,-1,+1,+3$, ideal thresholds lie near

\[-2,\quad0,\quad+2.\]

Real systems calibrate thresholds to account for

Part VIII — Timing closure and physical implementation

35. Static timing analysis

Digital support logic must meet setup and hold requirements.

For a synchronous path,

\[t_{clk} \ge t_{cq}+t_{comb}+t_{setup}+t_{skew}+t_{uncertainty}.\]

Hold requires the earliest data transition not to arrive before the receiving element’s hold window.

36. PrimeTime and NanoTime concepts

Industry timing signoff tools analyze

PrimeTime is widely used for static timing analysis.

NanoTime-class transistor-level timing analysis is used where standard-cell timing abstraction is insufficient, particularly around custom high-speed macros.

The key concept is not tool syntax but understanding the timing graph, constraints, corners, and signoff assumptions.

37. Clock-domain crossing

SerDes contains multiple clock domains.

CDC structures include

Improper CDC design can produce failures that appear only rarely and are difficult to reproduce in the lab.

Part IX — Modeling and verification

38. SystemVerilog real-number modeling

RNM represents analog quantities using real-valued variables inside event-driven simulation.

It is much faster than transistor-level simulation for full-chip verification.

Models should include the nonidealities relevant to the digital system, such as

39. Verilog-AMS

Verilog-AMS supports analog and mixed-signal behavioral modeling with continuous-time equations.

It is useful when analog dynamics, electrical nodes, and event-driven digital control must coexist.

40. MATLAB and Python models

System-level link models can include

\[\text{bits} \rightarrow \text{TX FFE} \rightarrow \text{channel} \rightarrow \text{noise/jitter} \rightarrow \text{RX EQ} \rightarrow \text{CDR} \rightarrow BER.\]

These models are ideal for rapid architecture exploration before transistor implementation.

41. Correlating model hierarchy

A robust hierarchy is

\[\boxed{ \text{behavioral model} \leftrightarrow \text{transistor simulation} \leftrightarrow \text{post-layout} \leftrightarrow \text{lab data}. }\]

Each level should have clearly defined observables and tolerances.

Part X — Protocol context

42. PCI Express

PCIe is a point-to-point differential serial link.

Key SerDes concepts include

PCIe 6.0 and later use PAM4, making advanced equalization and FEC/FLIT architecture relevant.

See Signal Integrity & Power Integrity.

43. USB

USB 3.x and USB4 use high-speed differential serial links over the USB-C ecosystem.

Important implementation concerns include

See Signal Integrity & Power Integrity.

44. DisplayPort

DisplayPort transports high-bandwidth video over multiple serial lanes.

SerDes concerns include

45. M-PHY

MIPI M-PHY is a high-speed serial physical layer used in mobile and embedded ecosystems, including applications such as UFS and UniPro-based links.

Important concepts include

Protocol implementations differ, but the same analog foundations—termination, equalization, jitter, CDR, adaptation, and PVT calibration—remain reusable.

Part XI — Lab validation and production

46. SerDes bench setup

Typical equipment includes

Fixture and cable de-embedding are essential when the measurement reference plane differs from the silicon/package boundary.

47. TX characterization

Measure

48. RX characterization

Measure

49. PVT and shmoo characterization

A shmoo plot maps pass/fail over two operating variables.

Examples include

\[V_{DD}\times f, \qquad T\times V_{DD}, \qquad \text{channel loss}\times\text{jitter}.\]

Shmoo testing reveals guard-band and failure-boundary structure that a few nominal test points cannot show.

50. Failure debug

A useful decomposition is

\[\text{failure} \rightarrow \begin{cases} \text{channel / SI}\\ \text{TX}\\ \text{RX / EQ}\\ \text{clock / CDR}\\ \text{power / supply noise}\\ \text{digital control / adaptation} \end{cases}\]

The fastest debugging comes from selecting measurements that isolate these categories.

Part XII — IP development and delivery

51. From architecture to IP requirement

A high-speed IO IP block needs explicit requirements for

These requirements should be quantitatively traceable to system needs.

52. IP signoff and quality checks

Typical deliverables/checks include

A reusable SerDes IP block is a product within the SoC project.

53. Cross-functional development

High-speed IO requires continuous interaction among

Many failures occur at interfaces between teams rather than inside an isolated schematic.

Part XIII — Scripting and automation

54. Useful automation targets

Python, MATLAB, Tcl, shell, or EDA-specific scripting can automate

A repeatable automated flow is itself an engineering asset.

55. Data-analysis pipeline

A useful lab pipeline is

\[\boxed{ \text{instrument} \rightarrow \text{raw waveform / BER} \rightarrow \text{automated extraction} \rightarrow \text{corner database} \rightarrow \text{plots / limits / correlation}. }\]

Keep raw data, analysis code, calibration metadata, and firmware/IP revision linked so results remain reproducible.

56. Relationship to the rest of this reference

High-speed SerDes sits at the intersection of

\[\boxed{ \text{analog IC} + \text{digital timing} + \text{RF / transmission lines} + \text{SI/PI} + \text{control / adaptation} }.\]

That intersection is exactly why SerDes design is a demanding mixed-signal discipline.

Board-level interface implementation

For PCIe/USB/Thunderbolt/HDMI PCB channels, connector launches, controlled impedance, via stubs, backdrilling, flex/rigid-flex routing and CAD/bring-up workflow, see Hardware Interfaces & PCB/Flex Design.

Related: Analog Mixed-Signal IC Design · Silicon Interfaces & SoC Implementation · Signal Integrity & Power Integrity · RF & Microwave · Measurements · Computational Methods