EM Applications of ElectromagneticsBuilt using ChatGPT · Connected engineering reference
Home › Hardware Interfaces & PCB/Flex Design
On this page

Hardware Interfaces & PCB/Flex Design

30-second intuition“Proficiency in PCIe, USB, I²C, Thunderbolt, SPI, UART and HDMI” means more than knowing protocol names. You should understand what signals exist, how the link initializes, what the electrical channel requires, how it is laid out on a PCB/flex, what commonly fails, and how to debug it with instruments and protocol tools. Strong PCB/flex knowledge means you can turn those interface requirements into stackup, constraints, placement, routing, power delivery, manufacturing data and a board that passes bring-up.
interface specification→schematic + constraints→PCB / flex layout→SI/PI + DRC/DFM→bring-up + compliance

Part I — Interface map

1. What you should know at a glance

Interface Physical style Main use Hardware topics to know
PCIe high-speed differential serial lanes CPU/SoC ↔ GPU, SSD, NIC, accelerator lanes, LTSSM, equalization, refclk, PERST#, channel loss, retimers
USB USB2 differential + SuperSpeed pairs; often USB-C peripherals, storage, charging, tunneling USB2 vs USB3/USB4, Type-C, CC, PD, orientation mux, ESD, retimers
Thunderbolt high-speed USB-C cable interface PCIe/DisplayPort/USB tunneling controllers, USB4 relation, bandwidth, security, PD, cable/retimer design
I²C 2-wire open-drain bus sensors, PMICs, EEPROM, control pull-ups, capacitance, addressing, ACK/NACK, arbitration, clock stretching
SPI synchronous single-ended point-to-point/multi-target flash, ADC/DAC, RF ICs, displays CPOL/CPHA, chip-select, timing, edge rate, fanout, termination
UART asynchronous TX/RX debug, GPS, modules, MCU links baud rate, framing, level standards, clock mismatch
HDMI high-speed differential video/audio link display interface TMDS/FRL, DDC, HPD, eARC, ESD, connector/launch quality

Part II — PCI Express

2. PCIe architecture

A PCIe link is built from one or more bidirectional serial lanes.

Common widths are

\[x1,quad x2,quad x4,quad x8,quad x16.\]

Each lane contains a transmit and receive differential pair.

Conceptually,

\[\boxed{ \text{Transaction Layer} \rightarrow \text{Data Link Layer} \rightarrow \text{Physical Layer} \rightarrow \text{PCB / connector channel} }\]

The PHY handles serialization, equalization, clock recovery and lane behavior; the higher layers handle packets, flow control and configuration.

3. PCIe generations

Generation Raw rate per lane Signaling
PCIe 3.0 8 GT/s NRZ
PCIe 4.0 16 GT/s NRZ
PCIe 5.0 32 GT/s NRZ
PCIe 6.x 64 GT/s PAM4 + FLIT/FEC
PCIe 7.x 128 GT/s PAM4

PCI-SIG lists PCI Express Base Specification Revision 7.1 as the current approved base specification as of September 2026.

Official reference: PCI-SIG PCI Express Specifications.

4. Signals you should recognize

Beyond the differential data lanes, a platform may include

For M.2 or add-in cards, the connector specification adds mechanical and power constraints.

PCIe does not simply begin sending application data after power-up.

The LTSSM moves through states such as

A board that enumerates at Gen3 but not Gen5 may have a channel/equalization problem rather than a software problem.

6. PCIe equalization

At high speed, the channel attenuates high-frequency components.

The link uses combinations of

For PCIe 6.0 and later, PAM4 makes vertical noise margin smaller and FEC/FLIT operation becomes part of the architecture.

PCI-SIG’s PCIe 6.0 overview documents 64 GT/s, PAM4, FLIT mode and lightweight FEC. PCIe 6.0 overview.

7. PCIe PCB layout

Key rules:

The exact target impedance/tolerance comes from the applicable PCIe/CEM/platform specification and stackup.

8. PCIe debug

Useful tools include

Useful questions:

  1. Does the device enumerate?
  2. At what negotiated generation and width?
  3. Is the link down-training?
  4. Does Recovery occur repeatedly?
  5. Are errors lane-specific?
  6. Is the problem channel loss, REFCLK/jitter, power, reset, firmware, or protocol?

Part III — USB and USB Type-C

9. USB is not the same as USB-C

USB-C is a connector system.

A USB-C port can carry different combinations of

Do not infer speed merely from connector shape.

10. USB speed families

Technology Nominal data rate
USB 2.0 High-Speed 480 Mb/s
USB 3.2 Gen 1 5 Gb/s
USB 3.2 Gen 2 10 Gb/s
USB 3.2 Gen 2x2 20 Gb/s
USB4 up to 40 Gb/s class
USB4 Version 2.0 80 Gb/s class with higher asymmetric capability

The current USB4 Version 2.0 specification was published by USB-IF in April 2026.

Official: USB4 Specification v2.0.

11. USB-C signals

Important USB-C pins/signals include

The CC pins establish

Current official reference: USB Type-C Cable and Connector Specification Release 2.5.

12. USB Power Delivery

USB PD negotiates voltage/current over the Type-C ecosystem.

Board-level considerations include

High-speed data and high-power delivery coexist physically, so SI, PI and thermal design interact.

13. USB PCB layout

For SuperSpeed/USB4 paths:

USB2 D+/D− routing is less demanding than USB4 but still benefits from controlled geometry and clean return paths.

Part IV — Thunderbolt

14. What Thunderbolt is

Thunderbolt uses the USB-C connector ecosystem and transports high-performance data/display traffic.

Thunderbolt 5 supports USB4 compatibility and can carry

Intel specifies Thunderbolt 5 links at up to 80 Gb/s bidirectional, with bandwidth boost modes reaching up to 120 Gb/s in one direction for display-intensive use cases.

Official overview: Intel Thunderbolt Technology.

15. What matters in a Thunderbolt design

Know the system around the controller:

Thunderbolt is therefore a system integration problem, not merely four high-speed traces.

Part V — I²C

16. Electrical principle

I²C uses two lines:

\[\boxed{ SDA\quad \text{and}\quad SCL }\]

Standard I²C uses open-drain/open-collector signaling.

Devices pull the line LOW; external resistors pull it HIGH.

This allows wired-AND behavior and arbitration.

17. I²C speed modes

NXP’s UM10204 defines:

Mode Data rate
Standard-mode 100 kbit/s
Fast-mode 400 kbit/s
Fast-mode Plus 1 Mbit/s
High-speed mode 3.4 Mbit/s
Ultra Fast-mode 5 Mbit/s, unidirectional

Official reference: NXP UM10204 — I²C-bus specification.

18. Pull-up resistor tradeoff

The bus rise time is approximately related to

\[\tau\sim R_P C_B.\]

A pull-up that is too large gives slow edges.

A pull-up that is too small requires excessive sink current.

Therefore choose $R_P$ from

19. I²C protocol concepts

Know

Common problems are incorrect address, missing pull-ups, wrong voltage level, excessive bus capacitance and a target holding SDA low.

Part VI — SPI

20. SPI signals

A typical SPI bus contains

SPI is normally push-pull and synchronous.

Unlike I²C, there is no universal central SPI standard defining one maximum speed or one connector.

Always read the device datasheet.

21. CPOL and CPHA

The four common SPI modes are defined from

A controller and target using different modes can produce completely plausible-looking clocks but corrupted data.

22. SPI PCB issues

At low speed SPI behaves like ordinary digital logic.

At fast edge rates it becomes a transmission-line problem.

Watch

The edge rate, not merely the clock frequency, tells you when SI becomes important.

Part VII — UART

23. UART basics

UART is asynchronous.

A typical frame contains

\[\boxed{ \text{start} + \text{data} + \text{optional parity} + \text{stop}. }\]

Both ends must agree on baud rate and framing.

24. UART is not RS-232

UART describes the logical serial framing/peripheral.

Electrical standards such as

use different voltage levels and drivers.

Do not connect an MCU UART pin directly to an RS-232 voltage-level interface without a transceiver.

25. UART debug

Use

Check

Part VIII — HDMI

26. HDMI architecture

HDMI transports uncompressed/digitally encoded video and audio plus control/management channels.

Modern HDMI includes

Older HDMI generations use TMDS; newer high-rate modes use Fixed Rate Link (FRL).

27. HDMI 2.2

HDMI Forum released HDMI 2.2 in June 2025.

Its headline maximum bandwidth is 96 Gb/s, with higher-resolution/high-refresh display modes and next-generation FRL.

Official overview: HDMI 2.2 Specification.

28. HDMI board layout

Important concerns include

For high-rate HDMI, connector region layout and ESD selection can determine whether a nominally correct schematic passes compliance.

Part IX — High-speed PCB design

29. Start with stackup

Do not route first and “calculate impedance later.”

The stackup determines

A strong workflow is

\[\boxed{ \text{fabricator stackup} \rightarrow \text{impedance targets} \rightarrow \text{routing rules} \rightarrow \text{SI verification}. }\]

30. Controlled impedance

For high-speed links, trace geometry and dielectric construction are chosen for a target impedance.

Typical design types:

Do not copy trace width from another PCB: impedance depends on the actual stackup.

31. Return current

High-frequency return current flows near the signal path on its reference plane.

A split/gap under a high-speed trace forces the return current to detour, increasing loop inductance and radiation.

Therefore:

Route high-speed signals over continuous reference planes.

When changing reference planes, provide an intentional return-current transition.

32. Differential pairs

Important quantities include

Avoid obsessing over geometrical symmetry while ignoring the complete electromagnetic channel.

A differential pair still needs a good reference plane.

33. Length versus delay matching

Equal physical length does not always mean equal electrical delay.

Delay depends on

\[t_d=\frac{l}{v_p}.\]

If traces use different layers with different effective permittivity, time-domain matching may be more meaningful than simple length matching.

Current KiCad documentation explicitly supports both length- and delay-domain tuning for high-speed nets. KiCad PCB Editor.

34. Vias and stubs

A via is a 3-D discontinuity containing

At high data rates, unused stubs can create resonances.

Mitigations include

35. Connector and BGA breakout

The hardest part of a channel is often not the long uniform trace.

Pay special attention to

These localized discontinuities can dominate return loss.

36. Crosstalk

Coupling increases with

Mitigate through

37. Via stubs and backdrilling

Backdrilling removes unused plated-through-hole barrel beneath the active signal transition.

It is common in

It should be designed together with PCB fabrication capability and residual-stub limits.

Part X — Power integrity

38. Decoupling

A digital IC draws transient current.

The PDN must provide low impedance over the relevant frequency range.

A basic target is

\[\boxed{ Z_{target}=\frac{\Delta V_{allow}}{\Delta I}. }\]

Use

Do not select decoupling only by nominal capacitance; ESL/ESR and placement matter.

39. Power rails for high-speed interfaces

High-speed PHYs often have separate

supplies.

Noise coupling into PLL/CDR/SerDes rails can become jitter.

The PCB layout must therefore connect SI and PI thinking.

Part XI — Flex and rigid-flex

40. Why use flex

Flex is used when the product needs

A rigid-flex design combines rigid PCB regions and flexible interconnect in one fabricated structure.

41. Static versus dynamic flex

Two very different cases:

Flex-to-install

Bent during assembly and then mostly stationary.

Dynamic flex

Repeatedly moves during product life.

Dynamic flex requires substantially more conservative mechanical design.

IPC-6013 distinguishes installation-use and continuous-flex usage classes.

42. Flex layout rules

Good practice includes

Never choose a universal bend-radius rule without the material stackup and fabrication process.

43. Flex copper and materials

Flex constructions commonly use polyimide and may use rolled-annealed copper for improved repeated-flex behavior.

Important mechanical/electrical parameters include

A high-speed rigid-flex link must preserve both mechanical reliability and electrical impedance.

44. Flex standards

Two standards worth recognizing are

IPC explicitly identifies IPC-2223 for flexible/rigid-flex design and IPC-6013 for qualification/performance.

Official references:

Always check the revision required by your organization or fabricator.

Part XII — PCB design workflow

45. Schematic capture

A strong schematic includes

The schematic should communicate design intent, not merely connectivity.

46. Library quality

For each component verify

One bad footprint can invalidate an otherwise perfect circuit.

47. Constraint management

Create constraints before detailed routing.

Examples:

Professional PCB design is heavily constraint-driven.

48. Placement

Placement determines most of the eventual routing quality.

Prioritize

  1. connectors;
  2. processors/FPGAs/SoCs;
  3. memories;
  4. SerDes/PHY devices;
  5. regulators;
  6. clocks;
  7. decoupling;
  8. remaining support circuitry.

Place the topology before drawing traces.

49. Routing order

A useful priority is

  1. clocks / reference;
  2. highest-speed serial interfaces;
  3. DDR/source-synchronous memory;
  4. sensitive analog/RF;
  5. power;
  6. lower-speed digital/control.

The exact order depends on system architecture, but not all nets are equal.

50. Fabrication outputs

Know how to generate/review

A PCB is not finished when routing ends; it is finished when fabrication and assembly intent is unambiguous.

Part XIII — CAD tools

51. Altium Designer

Common in product-development teams.

Know

Altium’s current rigid-flex documentation covers substacks, board regions and bend definitions. Altium rigid-flex design.

52. Cadence OrCAD / Allegro

Widely used for complex/high-speed commercial electronics.

Important concepts include

The skill that transfers between CAD packages is constraint-driven board design, not memorizing menu locations.

53. Siemens Xpedition

Xpedition targets high-density and advanced PCB systems.

Siemens describes current Xpedition Advanced capabilities including

Official: Siemens Xpedition Advanced.

Rigid-flex reference: Siemens Xpedition rigid-flex design.

54. KiCad

KiCad is a capable open-source PCB platform.

Its PCB editor supports

Official: KiCad PCB Editor.

55. SI/PI and electromagnetic tools

CAD layout is only one layer.

Useful analysis tools include

Know what problem requires 2-D/3-D extraction versus a simple transmission-line model.

Part XIV — Bring-up and debug

56. Board bring-up order

A disciplined sequence is

\[\boxed{ \text{shorts} \rightarrow \text{power rails} \rightarrow \text{clocks} \rightarrow \text{reset} \rightarrow \text{JTAG/debug} \rightarrow \text{low-speed buses} \rightarrow \text{high-speed links}. }\]

Do not begin by blaming PCIe if the PHY PLL supply is wrong.

57. Instruments you should be comfortable with

Instrument Use
DMM rails, resistance, continuity
Oscilloscope clocks, power noise, eye/jitter, signal quality
Logic analyzer I²C/SPI/UART/protocol timing
TDR/TDT impedance/discontinuities
VNA channel S-parameters
BERT BER/jitter tolerance
Protocol analyzer PCIe/USB/Thunderbolt transaction/link debug
Current probe rail/load/transient behavior

58. Common failure patterns

PCIe

USB / Thunderbolt

I²C

SPI

UART

HDMI

Part XV — What “proficiency” should mean

59. Interface proficiency

You should be able to explain for each interface:

60. PCB/flex proficiency

You should be able to

61. Interview-level summary

A strong answer to “Do you know PCIe/USB/I²C/SPI/UART/HDMI and PCB layout?” should connect protocol and physical design:

A digital interface is only reliable when its protocol, PHY, clocking, power, connector and PCB channel are designed together. For high-speed interfaces I treat the package, vias, traces, connectors and cable as one channel, define stackup/impedance and loss constraints before routing, and validate with SI tools and measurements. For low-speed buses I still check voltage levels, pull-ups, timing and edge integrity. For flex/rigid-flex I add mechanical bend, coverlay, stiffener and fabrication constraints to the electrical design.

Part XVI — Official and practical references

62. Interface specifications

SPI and UART are implemented across many device families rather than governed by one single modern public specification; use the controller/target device datasheets for timing and electrical limits.

63. PCB / flex references

Signal Integrity & Power Integrity · High-Speed SerDes & IO · Silicon Interfaces & SoC · ADC & DAC · Arduino Boards · Measurements & Instruments

See Ansys Electronics & Semiconductor Software for HFSS, SIwave, Q3D, Icepak, HFSS-IC and chip/package workflows.